Conventional semiconductor chip or die packaging techniques comprise bonding a semiconductor chip to a die-attach pad secured by tie bars and then sealing by synthetic resin molding, whereby the resulting semiconductor device or package is formed. As the geometry of transistors continues to plunge into the deep sub-micron regime, plastic packaging of integrated circuits presents greater challenges to manufacturers. The reduction in the transistor size results in a smaller die with a reduced perimeter around its edges for securing bond pads which provide input/output connections to external circuitry. Each bond pad on the die is connected to an internal package lead for transferring electrical signals between the integrated circuit and external circuitry.
Conventional lead frame designs are attendant with various problems. As the geometric size of a die shrinks, at least three problems are exacerbated. Firstly, as the die shrinks in size, there is less perimeter around the die, resulting in tighter bond pad pitch. To accommodate this tighter bond pad pitch, finer diameter bond wires are conventionally used, e.g., down to about 0.9 mil. However, finer diameter wires tend to sweep to a greater degree than thickner wires during molding, thereby generating greater shorts. Secondly, there are manufacturing limits to the minimum lead frame pitch at a given lead width. Accordingly, as the die is reduced in size, the lead fingers cannot be moved proportionately, thereby resulting in longer wires. Longer wires are more vulnerable to sweep than shorter wires, thereby increasing shorts. The phenomenon known as wire sweep occurs in packaging integrated circuit devices and is particularly acute at the corner of a die because the distance between each of the corners of a polygonal lead frame and an adjacent bonding pad on the circuit chip tends to be the longest.
Conventional approaches to minimizing wire sweep and crossing involve increasing the bond pad pitch proximate the corners of the die-attach pad. However, greater bond pad pitch proximate the corners increase the dimensions of the chip, thereby increasing manufacturing costs. Another conventional approach is to shorten the bond wires by reducing the width of a metal lead. This approach, however, compromises the overall yield of wire bonding semiconductor chips and increases lead frame manufacturing costs.
Accordingly, there exists a need for a lead frame design that minimizes or eliminates electrical shorting, particularly due to mold sweep. There exists a particular need for such a lead frame design suitable for use with a submicron integrated circuit die.